RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience

Ruicong Chen, Hanrui Wang, Anantha Chandrakasan, Hae-Seung Lee
MIT
(* indicates equal contribution)

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  • 2022-06-14

    RaM-SAR is covered by MIT News.

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Abstract

This paper presents RaM-SAR, a 12b 25MS/s 11.3fJ/conv.-step secure random-mapping SAR ADC with power and EM side-channel attack resilience. Each conversion is randomly mapped to one of the thousands of conversion sequences to randomize power supply traces. This technique protects against neural network based power and EM side-channel attacks. It enables protection with much lower energy and area overheads compared to the prior works. A prototype in 65nm CMOS demonstrates significant improvements with 12.5× higher bandwidth and 4.8× better energy-efficiency over prior works.

Framework Overview

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Citation

@INPROCEEDINGS{9830365,
 author={Chen, Ruicong and Wang, Hanrui and Chandrakasan, Anantha and Lee, Hae-Seung},
 booktitle={2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)},
 title={RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience},
 year={2022},
 volume={},
 number={},
 pages={94-95},
 keywords={Power supplies;Neural networks;Prototypes;Side-channel attacks;Bandwidth;Very large scale integration;Energy efficiency},
 doi={10.1109/VLSITechnologyandCir46769.2022.9830365}}

Acknowledgment

This research was supported by DARPA and Navy-ONR under contract N00014-20-1-4005 and MIT Center for Integrated Circuits and Systems. The authors thank Prof. Song Han and Maitreyi Ashok at MIT for their support and feedback.

Team Members